Increasing a data bandwidth from a core processor to a memory is a known issue in conventional digital signal processor devices. Demands of the core processor for data typically result in device designs that have wide busses and large memories to support the demands. The growth of the memories and the bus widths have drawback effects on an area, a wire density, a power consumption and a maximum clock frequency of the devices. The disadvantages contradict the purpose of improving the overall performance of the device.
It would be desirable to implement a representation of data relative to varying thresholds.